VLSI career roadmap: from ECE student to chip engineer
Every job in making a chip, what each one does, and exactly what to learn for it. Start here if you want a VLSI job in India.
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The 5 steps
How a chip is made, and where each job fits
ArchitectRTL designWrite the logic in Verilog / SV
RTL design engineerVerificationProve the design works
DV engineerSynthesis & DFTTurn RTL into gates; add test logic
DFT engineerPhysical designFloorplan, place, clock tree, route
PD engineerSignoffTiming (STA), DRC/LVS, power checks
STA / PD engineerFabPrint the chip on silicon wafers
Process / fab engineerPackaging & testCut, pack and test every chip
Test / packaging engineer
Pick your track
Design Verification (DV)Full guide
Find bugs in the design before the chip is made. Most fresher openings are here.
- Learn
- SystemVerilog, UVM, assertions, coverage, a protocol (APB/AXI/UART), scripting.
- Tools
- EDA Playground, VCS / Xcelium / Questa
- Starter project
- UVM testbench for an APB slave or UART
RTL DesignFull guide
Write the Verilog/SystemVerilog that becomes the logic inside a chip.
- Learn
- Digital design, synthesizable Verilog, FSMs, CDC, FIFOs, timing basics, a bus protocol.
- Tools
- Icarus / Verilator, Yosys; Design Compiler / Genus at work
- Starter project
- Async FIFO, UART, a small RISC-V core
Physical Design (PD)Full guide
Turn the gate-level netlist into a real layout that meets timing, power and area.
- Learn
- CMOS basics, floorplan, placement, clock tree synthesis, routing, STA (setup/hold), DRC/LVS, TCL scripting.
- Tools
- OpenLane / OpenROAD (free); Innovus, ICC2, PrimeTime at work
- Starter project
- Run a small design (e.g. a counter or UART) through OpenLane to GDSII and explain the timing report
DFT (Design for Test)Full guide
Add test logic so every manufactured chip can be tested quickly for defects.
- Learn
- Scan chains, ATPG, stuck-at and transition faults, MBIST, JTAG, compression, basic STA.
- Tools
- Synopsys TestMAX / Tessent at work; learn concepts with open examples
- Starter project
- Insert a scan chain in a small design and explain coverage and test time
Analog / Mixed-signal & LayoutFull guide
Design or lay out circuits like amplifiers, ADCs, PLLs and memories.
- Learn
- Device physics, MOSFET operation, op-amps, current mirrors, matching, parasitics; for layout: DRC/LVS, floorplanning of analog blocks.
- Tools
- ngspice, Xschem, Magic, KLayout (free); Cadence Virtuoso at work
- Starter project
- Design and simulate a two-stage op-amp or a simple bandgap; draw its layout in Magic
Embedded / FirmwareFull guide
Write the software that runs on chips and boards: drivers, RTOS and bring-up.
- Learn
- Embedded C, microcontrollers, UART/SPI/I2C, interrupts, RTOS basics, debugging with a logic analyser and oscilloscope.
- Tools
- ESP32 / STM32 / Arduino, GCC, FreeRTOS, Git
- Starter project
- A sensor node with an RTOS and a custom SPI/I2C driver
Not sure which track? Quick guide
Foundations everyone needs first
- Digital electronics: logic gates, K-maps, flip-flops, counters, FSMs, setup and hold time.
- CMOS basics: how a MOSFET works, an inverter, delay and power.
- Verilog: enough to write and simulate small circuits. Start with our Verilog questions.
- Linux and scripting: basic shell commands and a little Python or TCL. Every chip team uses them daily.
- New to chips? Read what a semiconductor is and how a chip is made.
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