14 SystemVerilog Assertions (SVA) and Coverage Interview Questions
Assertion and coverage questions with ready-to-use SVA code, plus the coverage questions interviewers use to check your verification thinking.
Updated 05 November 2026 · Written by Semicon Weekly in our own words · 14 questions
Practise these 14 questions free : type, speak or pick from 4 options and get an instant AI score.
Start practising → Questions on this page Difference between immediate and concurrent assertions? Explain overlapped |-> and non-overlapped |=> implication. What are $rose, $fell, $stable and $past? Difference between @(posedge sig) and $rose(sig)? Write an assertion: once req goes high, gnt must come within 1 to 5 cycles. Assertion: a 5-bit grant must be one-hot (or all zero) at every clock. Write an assertion that an output never goes X or Z. Signal a must stay high for at least 3 cycles once it rises. When a is asserted, b must be asserted and stay high until c arrives. How do you disable an assertion during reset? How do you turn off all assertions? For a FIFO, write assertions: no write when full, and full and empty never both high. Where do you write assertions in a UVM testbench? Difference between code coverage and functional coverage? What are bins, cross coverage, ignore_bins and illegal_bins? Code coverage is near 100% but functional coverage is only 60%. What does it mean? And the reverse? easy Basics theory
1. Difference between immediate and concurrent assertions?Show answer Immediate: checks a condition at that point in procedural code, like an if (assert (x)) concurrent: checks a property over clock cycles, sampled on a clock (in the Preponed region), runs in parallel, uses sequences Answer this in the AI interview bot → easy Implication theory
2. Explain overlapped |-> and non-overlapped |=> implication.Show answer |-> : if antecedent matches, check consequent in the SAME cycle; |=> : check consequent starting the NEXT cycle (same as |-> ##1); if antecedent does not match, the property is vacuously true
Common mistake: Not knowing vacuous pass
Answer this in the AI interview bot → medium Functions theory
3. What are $rose, $fell, $stable and $past? Difference between @(posedge sig) and $rose(sig)?Show answer $rose: signal went 0 to 1 between previous and current sample $fell: 1 to 0 $stable: unchanged $past(sig, n): value n cycles ago @(posedge sig) is an event that wakes up immediately when sig changes $rose is evaluated only at the sampling clock edge Answer this in the AI interview bot → medium Scenarios code
4. Write an assertion: once req goes high, gnt must come within 1 to 5 cycles.Show answer property p; @(posedge clk) disable iff (rst) $rose(req) |-> ##[1:5] gnt; endproperty assert property (p);
Common mistake: Using req instead of $rose(req) so it re-triggers every cycle
Interviewer may ask next: How would you write 'gnt eventually' with no upper bound?
Answer this in the AI interview bot → medium Scenarios code
5. Assertion: a 5-bit grant must be one-hot (or all zero) at every clock.Show answer assert property (@(posedge clk) $onehot0(grant)); use $onehot if exactly one bit must be set
Answer this in the AI interview bot → easy Scenarios code
6. Write an assertion that an output never goes X or Z.Show answer assert property (@(posedge clk) disable iff (rst) !$isunknown(dout));
Answer this in the AI interview bot → medium Scenarios code
7. Signal a must stay high for at least 3 cycles once it rises.Show answer $rose(a) |-> a[*3]; (consecutive repetition)
Interviewer may ask next: What is the difference between [*3], [->3] and [=3]?
Answer this in the AI interview bot → medium Scenarios code
8. When a is asserted, b must be asserted and stay high until c arrives.Show answer $rose(a) |-> (b until_with c); until_with means b must hold up to and including the cycle where c is true; plain until stops checking b one cycle before c
Answer this in the AI interview bot → easy Control theory
9. How do you disable an assertion during reset? How do you turn off all assertions?Show answer Disable iff (rst) inside the property $assertoff / $asserton / $assertkill system tasks to control assertions globally or per hierarchy during simulation Answer this in the AI interview bot → medium FIFO code
10. For a FIFO, write assertions: no write when full, and full and empty never both high.Show answer assert property (@(posedge clk) disable iff (rst) full |-> !wr_en); (or check overflow flag) assert property (@(posedge clk) !(full && empty));
Interviewer may ask next: Write one for: after reset, empty must be 1.
Answer this in the AI interview bot → Reading is not enough. Say your answer out loud or type it, and get a score out of 10 with what you missed.
Practise free → medium Placement theory
11. Where do you write assertions in a UVM testbench?Show answer Not in UVM classes (classes cannot hold concurrent assertions) Put them in the interface, in a separate checker module bound to the DUT with bind, or in the RTL Protocol checks usually live in the interface Common mistake: Saying inside the monitor class
Answer this in the AI interview bot → easy Types theory
12. Difference between code coverage and functional coverage?Show answer Code coverage: automatic, measures which code was exercised (line/statement, branch, condition/expression, toggle, FSM) Functional coverage: user-written covergroups that measure whether the spec features/scenarios were exercised 100% code coverage does not mean the design is correct Answer this in the AI interview bot → medium Covergroups theory
13. What are bins, cross coverage, ignore_bins and illegal_bins?Show answer Bins group values of a coverpoint Cross covers combinations of two or more coverpoints Ignore_bins removes values from coverage calculation Illegal_bins flags an error if that value occurs Common mistake: Saying ignore and illegal are the same
Answer this in the AI interview bot → hard Closure scenario
14. Code coverage is near 100% but functional coverage is only 60%. What does it mean? And the reverse?Show answer High code + low functional: the code ran but important scenarios/combinations from the spec were not hit, so improve constraints or write directed tests High functional + low code: either the coverage plan is missing features, or there is dead/unreachable RTL code to review Answer this in the AI interview bot →