21 RTL Design Interview Questions: FSM, CDC, FIFO and Timing

• Combinational always block where some output is not assigned in every path (missing else / missing case default)
• bad: unintended storage, timing analysis problems, glitches, DFT issues
• avoid: default assignments at top of block, full if-else, case default, lint checks, always_comb

Common mistake: Saying latches are only caused by missing else

Interviewer may ask next: Is there any situation where a latch is intentionally used?

Sync: reset checked only on clock edge, always @(posedge clk) if (rst) q <= 0; Async: always @(posedge clk or posedge rst); async acts immediately without clock; sync is glitch-tolerant and timing-friendly but needs clock; async needs reset synchronizer for de-assertion (recovery/removal timing)

Common mistake: Putting rst in sensitivity list for sync reset

Interviewer may ask next: What is reset synchronization (async assert, sync de-assert)?

• They are setup/hold-like timing checks for an asynchronous reset de-assertion relative to the clock edge
• recovery: reset must be released some time BEFORE the clock edge
• removal: reset must stay asserted some time AFTER the clock edge
• Violation can cause metastability

Common mistake: Confusing them with normal setup/hold on D

States: IDLE, S1, S10, S101, S1011 (detect) = 5 states for Moore; on detection with overlap go to S1 or S10 based on next input (after 1011, last '1' can start a new match: from S1011 input 0 goes to S10, input 1 goes to S1); separate state register, next-state logic and output logic

Common mistake: Resetting to IDLE after detection (non-overlapping by mistake)

Interviewer may ask next: How many states does the Mealy version need and why one less?

• Moore output depends only on state, so it is glitch-free and registered-friendly but reacts one cycle later
• Mealy output depends on state and inputs, fewer states and faster response but output can glitch with input
• Registered Mealy outputs are common

Common mistake: Saying Moore always needs more flip-flops

• Binary: fewest flops (log2 N), more decode logic
• One-hot: N flops, very simple next-state logic, fast, good on FPGAs
• gray: only one bit changes between adjacent states, lower power and safer for sequential state machines
• Choice is area vs speed vs power

Interviewer may ask next: How would you make an FSM safe against illegal states?

• 1-block: everything in one clocked block, outputs become registered
• 2-block: clocked state register + combinational next-state/output
• 3-block: separate state register, next-state logic, output logic
• 2 or 3 block is preferred for readability and synthesis control

• When a flop samples data changing inside its setup/hold window its output can stay at an in-between level for an unknown time
• 2-flop synchronizer gives the first flop a full clock period to resolve before the second flop samples it, cutting failure probability (MTBF goes up a lot)
• Only for single-bit signals

Common mistake: Saying the synchronizer removes metastability completely

Interviewer may ask next: Why can you not use a 2-flop synchronizer on an 8-bit bus?

• Options: asynchronous FIFO with gray-coded pointers
• Handshake (req/ack) where data is held stable and only the control bit is synchronized
• MUX recirculation with a synchronized enable
• Gray coding for counters since only one bit changes at a time

Common mistake: Synchronizing each bit separately with 2-flops

Interviewer may ask next: Why are async FIFO pointers gray coded?

• First-in first-out buffer between producer and consumer
• full: no space, writing now causes overflow (data lost)
• empty: no data, reading causes underflow (garbage read)
• Detection with a count, or with an extra MSB on read/write pointers (same pointer bits but MSB differs = full
• All equal = empty)

Common mistake: Not knowing the extra-MSB pointer method

Interviewer may ask next: How would you calculate FIFO depth for a burst of 100 writes at 100 MHz with reads at 80 MHz?

• Burst time = 120 / 100 MHz = 1.2 us
• Words read in that time = 1.2 us x 50 MHz = 60
• Depth needed = 120 - 60 = 60

Common mistake: Using frequencies ratio without considering burst length

Interviewer may ask next: What if the read side reads only once every 2 read clocks?

always @(posedge clk or negedge rst_n) if (!rst_n) cnt <= 0; else if (en) cnt <= cnt + 1; uses non-blocking; wraps from 15 to 0 naturally

Common mistake: Using blocking assignment

Interviewer may ask next: Convert it into a mod-10 counter.

• Ring: one-hot pattern rotates, N flops give N states, must be preset to a 1
• Johnson (twisted ring): inverted last output fed back, N flops give 2N states, decoding needs only 2-input gates
• Both have unused illegal states to handle

Interviewer may ask next: Write a 4-bit Johnson counter.

Binary to gray: g = b ^ (b >> 1); Gray to binary: b[MSB] = g[MSB], b[i] = b[i+1] ^ g[i] (loop from MSB down), or b[i] = ^(g >> i)

Common mistake: Using gray-to-binary formula for both

Interviewer may ask next: Where are gray codes used in real chips?

Use an array input and assign y = in[sel]; for 5:1 use case with a default (sel values 5-7 must be handled to avoid latch/x); sel width = $clog2(N)

Common mistake: No default for unused sel values

Register din into din_d on the clock; rise = din & ~din_d; fall = ~din & din_d; any = din ^ din_d; if din is async, synchronize it first

Common mistake: Using posedge din directly as a clock

Interviewer may ask next: Make it detect both edges.

• Shift register whose input is XOR of selected taps
• With a primitive polynomial it cycles through 2^N - 1 states (all-zero is a lock-up state for XOR)
• Used for pseudo-random generation, BIST, CRC, scramblers

Common mistake: Saying it gives 2^N states

• Clock gating (enable-based, tool inserted ICG cells)
• Operand isolation (stop toggling of unused datapath)
• Avoid unnecessary toggles, gray coding for counters
• Memory power-down
• Multi-voltage and power gating at architecture level
• Dynamic power = a C V^2 f

Common mistake: Mentioning only clock gating

Interviewer may ask next: Why should you not write clock gating with a plain AND gate in RTL?

• Setup: data must be stable some time before the clock edge
• hold: data must stay stable some time after the edge
• Violation risks metastability or wrong capture
• Setup fixed by reducing logic delay or slowing the clock
• Hold does NOT depend on clock period and is fixed by adding delay

Common mistake: Saying hold violations are fixed by lowering frequency

Interviewer may ask next: Write the setup slack equation.

• Pipeline long paths
• Put late-arriving signals near the end of logic cones
• Avoid deep if-else priority chains
• Register module outputs
• Balance adder/mux trees
• Avoid combinational loops and gated clocks
• Resource sharing trades area for timing

• Scan insertion needs every flop controllable and observable from the test clock
• Loops create unknown states and cannot be scanned
• Generated/gated clocks must be bypassed with test-mode muxes
• Async resets also need control in test mode